This invention relates to managing signals in different clock domains and more particularly to a low gate count synchronizer circuit. This invention also relates to a low gate count programmable low-pass filter circuit.
Different clock signals are used to control different digital components on a circuit board. The different clock signals might operate in different clock domains. Clock signals operate in different clock domains when the clock signals are generated from independent sources. For example, a system clock might be generated from a clock circuit that is connected externally to a circuit board. A second reference clock might be generated locally on the circuit board with a crystal oscillator. The clock sources generate data signals that operate in different clock domains. The information that is to be passed between the two clock domains may be the data which is synchronized to the first clock, or the occurrence of the first clock itself.
Synchronizer circuits are used to prevent metastable conditions in devices that receive signals in different clock domains. The synchronizer circuits are located at each device requiring synchronization and typically synchronize the data to the clock signal driving the device. Complex synchronizer circuitry is necessary since a separate synchronizer circuit is needed for each device that requires synchronization and for each data line of each device.
Electrical lines often contain noise that can be mistakenly interpreted by digital circuitry as valid data. For example, network routers receive multiple network lines each carrying different signals. The signals on the network lines can be compromised by cross-talk and other noise conditions. If the noise is inadvertently processed as valid data, the router generates the wrong results or locks up.
Digital low pass filters can be used to remove noise from external serial data and clock lines. A standard circuit for filtering noise or xe2x80x9cglitchesxe2x80x9d from a signal uses a counter that is run off a system clock. When an input signal is asserted, the counter samples the input signal at the system clock rate. A comparator compares the counter value to a predetermined threshold value. When the counter value reaches the threshold value, the comparator generates an output signal representing a filtered equivalent of the input signal. These filter circuits require 10-20 bit counters for each data bit and only work off one edge of the input signal. Thus, the filter circuitry is complex, has limited accuracy and requires a large number of data lines.
Noise often has different frequencies and amplitude characteristics in different operating environments. A low pass filter might be effective at removing noise having one type of frequency or amplitude characteristic but ineffective at filtering noise having another frequency or amplitude characteristic. Digital circuitry also has different sensitivity to signal noise. For example, one digital circuit may not be effected by small glitches in an input signal while another digital circuit might reboot from the same glitch. Therefore, some input signals require more rigorous filtering than other input signals.
Accordingly, a need remains for a simple synchronizer circuit that converts data and clock signals into different clock domains and a simple digital filter that can be programmed for different operating conditions.
A synchronizer circuit manages signals in different clock domains by converting clock signals into pulses or xe2x80x9cticksxe2x80x9d. The pulses are generated according to a logic condition, such as a rising edge, that occurs in a first clock signal. The pulses are synchronized with a second clock signal operating in a second clock domain. Each pulse or xe2x80x9ctickxe2x80x9d is equivalent to a clock cycle of the first clock signal. If the frequency of the first clock signal is lowered, the pulses are generated less frequently. Digital circuitry is then driven at the frequency of the first clock and in the time domain of the second clock. This is achieved by using the pulses generated by the synchronizer circuit as clock enables while at the same time clocking the digital circuitry with the second clock signal. A handshaking protocol prevents the synchronizer circuit from going into a metastable condition while passing the first clock signal or data signal into a different time domain.
The synchronizer circuit includes a first stage that detects and latches the clock or data signal. A second stage generates clock pulses or data pulse corresponding with the first clock signal and synchronized with the second clock signal. A feedback circuit is coupled between the first stage and the second stage. The feedback circuit resets the first stage by using the output signal generated in the second stage. A multiplexer provides selective pulse generation from the synchronizer circuit.
In one embodiment of the invention, the synchronizer circuit is used in combination with a frequency measurement circuit for measuring the frequency of different external clock signals. The synchronizer circuit converts the external clock signals and a reference clock signal into clock pulses synchronized with a router system clock. The frequency measurement circuit then uses the pulses in different frequency modes to calculate the frequency of the network clock signals.
A programmable digital filter removes noise for data and clock signals. The digital filter includes multiple sampling stages that sample an input signal at multiple time intervals. A detection circuit is coupled to the sampling stages and changes the logic state of an output signal only when no noise is detected in the input signal. A control circuit is coupled to the sampling stages and selectively varies the time interval used by the filter for sampling the input signal.
The control circuit includes a multiplexer having multiple inputs each coupled to a different clock signal. The clock signal selected determines the selectable time interval used by the filter for detecting glitches having a different clock frequency. A synchronizer circuit is used to convert the different clock signals into clock pulses. The clock pulses are generated at the frequency of the selected clock signal and are synchronized with a system clock used for clocking the sampling stages. The pulses are used for enabling the sampling stages thereby selectively changing the time interval between each filter sample.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.